1. Field of the Invention
The present invention relates to a processor which installs a request master for performing a core function in accessing to a memory, and the processor which installs a memory control unit for controlling the accessing to the memory by arbitrating an access request to the memory by outputting the access request from the request master.
2. Background Arts
FIG. 16 is an extremely simplified diagram of a system comprising the processor and the memory, illustrating a conventional method of how a memory is being used. In the drawing of FIG. 16, a processor 1p is comprised of the following components: a request master 4p which performs a core function of data bus at an inner processor; and a memory control unit 3p for controlling an access to a memory 2 by arbitrating a request from the request master 4p. Also, the request master 4p installs a modulo addressing control unit 6p for cyclically accessing a specified memory area.
A conventional memory access operation for a case of accessing to the memory 2 is described next using FIG. 16. First, the request master 4p outputs a memory access request to the memory 2 situated outside through the memory control unit 3p. Normally, there are a plurality of request masters so that more than one memory access requests are simultaneously requested from the request masters. The memory control unit 3p arbitrates the plurality of memory access requests, chooses one of the requests, and commences accessing to the memory 2 situated outside. As described above, the access to the memory 2 is performed via the memory control unit 3p. The memory control unit 3p performs the memory access by specifying a start address and an end address received from the request master 4p.
In the conventional memory access, since an area on the memory 2 is set by specifying the start address and the end address, therefore, the area set is, for example, has a shape as illustrated in a shadowed area 400 on the memory 2 of FIG. 16. Also, when the modulo addressing control unit 6p operates effectively, in the conventional memory access, the area 400 is accessed a plurality of times, that is, the area 400 is cyclically accessed.
However, for media processors which are receiving much attention recently, such as a digital signal processor (DSP) which is specially geared for a multi-media processing tuned for efficiently performing a voice processing, a modem processing, or a compressed and elongated processing of an image. In DSP, a moving picture such as MPEG2 (Moving Picture Experts Group Phase 2) is commonly being dealt with. When dealing with the moving picture, as illustrated in 304 of FIG. 13, setting a square area in the memory would be convenient. The data of video screen is accessed by using one frame unit of 720.times.480 picture elements which is required to output the moving picture. Also, access requirement for the compressed and elongated processing is 8.times.8 block unit. Due to these, setting the square area in the memory is convenient. However, most of the processor cores installed in the media processors have a reduced instruction set computer (RISC) architecture, and there is no architecture available that is provided with an addressing mode for accessing the square area. On the other hand, there is a processor which installs a complexed instruction set computer (CISC) architecture provided with the addressing mode for accessing the square area. Although, a processing ability of the CISC architecture processor is not adequate enough to perform a high performance processing as those of a real time decode processing of MPEG2.
[Problems to be Solved by the Invention]
The conventional area specifying method of the memory accessing which sets the memory area by specifying the start address and the end address has a problem of not being able to specify the square area like the one illustrated in 304 of FIG. 13. Accordingly, the conventional memory accessing method results in an area like the one illustrated in FIG. 17. A hatching is implemented in areas 401, 402, 403 and 404. These areas are separately being used. The area 403 is a reused area which was previously used as an area that attaches to both the areas 402 and 404. The problem with the conventional area specifying method is that the memory cannot be used efficiently from an occurrence of small unused area 405 between the area 403 and the area 404, the occurrence of which depends on a size of the area 403.
Also, when specifying the square area, a plurality of rectangular areas 408 as illustrated in FIG. 18 are considered as one assembled unit of the rectangular areas 408. This leads to a problem of complexity in area control. Because, a start address 406 and an end address 407 are required in order to set each rectangular area. Further, a square area 409 must be taken as the assembled unit comprising the plurality of rectangular areas 408.
The present invention attempts to solve the problem mentioned above, and aims to obtain a processor having a memory control method for using the memory efficiently. Also, the present invention particularly focuses on a processor for accessing the square area of the memory.